The fabrication of semiconductor chips in industry is both a complex and lengthy process, involving the application of cutting edge nanotechnologies over a period of two to three months. \u00a0Of obvious importance is the research and design of the circuit architecture. However, the most poignant question is not \u201cwhat is to be made\u201d, but \u201chow it is to be made\u201d.\u00a0 It is through characterization, diagnostics and other yield learning tools that this question is answered.\u00a0 Defects that occur during fabrication can develop into fails, destroying the functionality of the semiconductor chip.\u00a0 Currently there are many methods of detecting these defects in order to analyze, define and \u201croot cause\u201d their origin. These methods include KLA optical devices, SEM failure analysis tools, and inline health monitors such as the LSM.<\/p>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 However, the more complex the logic of semiconductor chips becomes the more difficult the process is for translating the diagnostic data into a physical location.\u00a0 A promising solution to this problem is the analysis of volume logic diagnostic data.\u00a0 Using data from a wealth of other tools, optical pictures can be overlayed with wafer final test electrical data to produce the exact failing nets that occur from the detected defects.\u00a0 These locations will be submitted to failure analysis to gain hard evidence of the defect.\u00a0 Finally, several frequently occurring fails will be investigated with an understanding of the fabrication process to offer possible sources for the origin of the defect.<\/p>\n","protected":false},"excerpt":{"rendered":"
Benjamin Bayat. with Amy Eroh (IBM Burlington) \u00a0& Kathy KashVolume Logic Diagnostics on Microprocessor and ASICs Chips at IBM<\/p>\n
The fabrication of semiconductor chips in industry is both a complex and lengthy process, involving the application of cutting edge nanotechnologies over a period of two to three months. \u00a0Of obvious importance is the research and design of the circuit architecture. However, the most poignant question is not \u201cwhat is to be made\u201d, but \u201chow it is to be made\u201d.\u00a0 It is through characterization, diagnostics and other yield learning tools that this question is answered.\u00a0 Defects that occur during fabrication can develop into fails,<\/p>\n