Benjamin Bayat. with Amy Eroh (IBM Burlington)  & Kathy Kash

Volume Logic Diagnostics on Microprocessor and ASICs Chips at IBM

The fabrication of semiconductor chips in industry is both a complex and lengthy process, involving the application of cutting edge nanotechnologies over a period of two to three months.  Of obvious importance is the research and design of the circuit architecture. However, the most poignant question is not “what is to be made”, but “how it is to be made”.  It is through characterization, diagnostics and other yield learning tools that this question is answered.  Defects that occur during fabrication can develop into fails, destroying the functionality of the semiconductor chip.  Currently there are many methods of detecting these defects in order to analyze, define and “root cause” their origin. These methods include KLA optical devices, SEM failure analysis tools, and inline health monitors such as the LSM.

       However, the more complex the logic of semiconductor chips becomes the more difficult the process is for translating the diagnostic data into a physical location.  A promising solution to this problem is the analysis of volume logic diagnostic data.  Using data from a wealth of other tools, optical pictures can be overlayed with wafer final test electrical data to produce the exact failing nets that occur from the detected defects.  These locations will be submitted to failure analysis to gain hard evidence of the defect.  Finally, several frequently occurring fails will be investigated with an understanding of the fabrication process to offer possible sources for the origin of the defect.